The present invention pertains to a method for the fabrication of submicron, in width, trenches. Trenches are commonly used for the isolation of components on chips. At the present time these trenches are fabricated employing E beam or x-ray lithography, direct write on wafer or projection respectively. While the use of an E beam or x-rays results in narrow trenches these processes are very expensive, complicated and have very low throughput due to their complexity. Conventional optics are also employed for the fabrication of trenches. This is a less expensive and less time consuming method, but the resulting trenches are approximately 0.8 to 2 microns. These trenches are not only more difficult to refill and planarize, but due to their large size, require a large area of surface which results in larger products and is a waste of die area.
Prior art U.S. Pat. No. 4,449,287, entitled "Method of Providing a Narrow Groove or Slot in a Substrate Region, In Particular A Semiconductor Substrate Region", issued May 22, 1984, makes use of a spacer oxide which is similar to one used in the present invention, but which is realized in a different fashion. It is believed that a trench fabricated using this prior art, is limited to trenches greater than 0.5 m because of oxide encroachment from layer #7 and oxide expansion from oxide layer #3. Additionally, this prior art is more complicated and difficult to control.